USB host controller with DMA capability

ABSTRACT

An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.

This invention relates to a host controller, and in particular to a hostcontroller for use in a bus communications system.

The Universal Serial Bus (USB) specifications define a buscommunications system, in which a USB host can be connected to multipleUSB devices, in order to allow convenient data transfer between the USBhost and the USB devices. The invention relates more specifically to anEnhanced Host Controller Interface (EHCI) that acts as the interface fora host controller in a device which is acting as a USB host.

USB hosts are typically personal computers (PCs) or similar devices.That is, it is mainly PCs which are provided with the functionality toallow them to act as a USB host. This means that a conventional EHCIoperates in a situation in which there is a Peripheral ComponentInterconnect (PCI) standard bus, providing specific functionality, whichis used by the EHCI. For example, the EHCI uses the bus masteringfunctionality of the PCI to retrieve the data that is to be transmitted.

However, it is becoming recognized that it would be useful to allowother devices, for example such as mobile phones, to act as USB hosts.These other devices typically do not have a PCI bus, and so it is notpossible for the EHCI to take advantage of the PCI functionality.

Moreover, the host microprocessor in such devices typically has lessprocessing power than the microprocessor in a PC.

It would therefore be advantageous to provide a host controller for usein embedded applications, in which the PCI functionality is not assumed,and in which the demands on the host microprocessor are reduced.

According to a first aspect of the present invention, there is providedan embedded host controller, for use in a USB system comprising aprocessor and an associated system memory, wherein the host controllercomprises a DMA controller, and the host controller is adapted suchthat, in order to retrieve data from the associated system memory, astarting address and block length are sent to the DMA controller, andthe DMA controller is adapted such that, on receipt of a startingaddress and block length sent from the host controller, it retrieves theindicated data from the associated system memory.

This has the advantage that the embedded host controller can be usedwith different host microprocessors, without assuming that PCIfunctionality is available.

In a first preferred embodiment of the invention, wherein the hostcontroller allows bus arbitration, the DMA controller is adapted to senda bus request to the processor, and to retrieve data from the associatedsystem memory only when bus access has been granted.

In a second preferred embodiment of the invention, wherein the hostcontroller does not allow bus arbitration, the DMA controller is adaptedto send a signal to the processor while it is retrieving data from theassociated system memory, thereby preventing the processor fromsimultaneously attempting to access the associated system memory.

According to a second aspect of the present invention, there is provideda USB host, including a host controller in accordance with the firstaspect of the invention.

The invention will be described with reference to the accompanyingdrawings in which:

FIG. 1 is a block schematic diagram of a system including a firstembedded host controller in accordance with the present invention.

FIG. 2 is a block schematic diagram of a system including a secondembedded host controller in accordance with the present invention.

FIG. 1 is a block schematic diagram of a part of a USB host 10, inaccordance with the present invention. The term USB host is used hereinto mean a device which operates as a host in a system operating inaccordance with, for example, the USB 2.0 specification. That is, theUSB host can be connected by means of a USB bus to one or more USBdevices, and the USB host controls the communication of data to and fromthe USB devices.

The present invention is applicable to all USB hosts, but it isparticularly applicable to situations where the USB host is not apersonal computer, and so it does not have a Peripheral ComponentInterconnect (PCI) bus, and may not have an especially powerfulprocessor.

The USB host 10 has a host processor 20, a system memory 30, and a hostcontroller 40.

In this preferred embodiment of the invention, the processor 20 is anIntel® PXA210 or PXA250 processor, and as such is well known to theperson skilled in the art. Other processors having similar functionalitycan of course also be used. The processor 20 includes a General PurposeInput-Output (GPIO) block 22, and a memory controller 24. Other featuresand functions of the processor 20 will not be described further herein,except insofar as they are relevant to an understanding of the presentinvention.

The memory 30 is a SDRAM bank, which again, is well known to the personskilled in the art.

As is conventional, the host controller, or embedded EHCI host, 40 isadapted to retrieve data which is prepared by the processor 20 in asuitable format, and to transmit the data over the bus interface. In USBcommunications, there are two categories of data transfer, namelyasynchronous transfer and periodic transfer. Control and bulk data aretransmitted using asynchronous transfer, and ISO and interrupt data aretransmitted using periodic transfer. The Enhanced Host ControllerInterface (EHCI) uses a Queue Transaction Descriptor (qTD) datastructure for asynchronous transfer, and an Isochronous TransactionDescriptor (iTD) data structure for periodic transfer.

The processor 20 prepares the data in the appropriate structure, andstores it in the system memory 30, and the host controller 40 must thenretrieve the data from the system memory 30.

FIG. 1 shows in more detail the structure of the host controller 40. Thehost controller 40 includes an EHCI core 42, which is generallyconventional, and includes capability registers 44 and operationalregisters 46, but will not be described further herein. The hostcontroller 40 is connected to an address decoder 48, which is alsogenerally conventional.

The internal capability registers 44 and operational registers 46 of theEHCI core 42 can be implemented as a direct input/output map, and a CSsignal from the processor 20 can be used to select the embedded hostcontroller.

In accordance with the invention, the host controller 40 includes aDMA/bus master engine 50, which is adapted for the case where, as here,the processor 20 allows for some form of bus arbitration.

The EHCI core 42 of the host controller 40 uses the same transferdescriptors which are used in the conventional EHCI host controller,which retrieves data by mastering a PCI bus, and so the additionaleffort required to produce the EHCI core software is reduced.

The DMA/bus master engine 50 includes a SDRAM controller 52 and a directmemory access (DMA) master engine 54, and can be programmed with a startaddress 56 and a block length 58 by the EHCI core 42.

The DMA/bus master engine 50 can also receive inputs from a programmablebus release block 60.

The host controller 40 further includes a RAM 62.

The host controller 40 can access the processor 20 through direct inputsor outputs to or from the GPIO block 22, and can access the embeddedsystem memory bus 70.

When the host controller 40 is to retrieve the data from the systemmemory 30, the processor 20 must release the bus 70, allowing the hostcontroller 40 to access the system memory 30.

Thus, when the host controller 40 initializes a transfer of data, astarting address and block length are sent from the core logic 42 to theDMA controller 54, which issues a bus request to the GPIO block 22. TheGPIO block 22 sends a memory bus request (MBREQ) signal to the memorycontroller 24. When access is granted, a memory bus grant (MBGNT) signalis sent from the memory controller 24 to the GPIO block 22, which sendsa corresponding signal to the host controller 40. All of the data,address and control signal lines of the bus 70 are then tri-stated, suchthat the host controller 40 can access the memory 30. Data can then betransferred from the system memory 30 to the host controller 40 withoutrequiring further intervention from the processor 20.

Specifically, the DMA controller 54 bursts a block of data from thesystem memory 30 to the RAM 62, from which it can be transmitted overthe USB bus interface.

The SDRAM controller 52 provides refresh capability during the time whenthe bus 70 is granted to the host controller 40. That is, if the burstcycle/length is longer than the refresh period of the SDRAM 30, theSDRAM controller 52 performs the refresh function. This means that theburst length need not be restricted to the refresh period. Without theSDRAM controller 52 to perform the refresh function, it would benecessary to transfer bus utilization back to the processor 20 for it toperform the refresh function, and then back to the host controller 40 toresume data transfer.

The programmable bus release block 60 can be programmed by the processor20 with a number of clock cycles, and this sets the number of clockcycles for which the host controller 40 can occupy the bus 70 followinga single memory bus access grant. Thus, the programmed number of clockcycles indicates a maximum duration of a bus access. Once thisprogrammed number of clock cycles has expired, the host controller 40,by means of the DMA controller 54, performs a last dataword transfer,and then releases the bus 70 by means of a de-assertion bus request.

This prevents the host controller from occupying the bus 70 for so longthat it prevents the processor 20 from performing critical tasks, andtherefore allows a better balance of bus utilization between theprocessor 20 and host controller 40.

Thus, FIG. 1 shows an architecture which is applicable in the case wherethe processor 20 provides a form of bus arbitration, allowing release ofits data bus. By contrast, FIG. 2 shows an architecture which isapplicable in the case where the processor does not provide busarbitration.

The USB host 110 has a host processor 120, a system memory 130, and ahost controller 140.

In this case, the processor 120 is of a type which does not allow busarbitration. Features and functions of the processor 120 will not bedescribed further herein, except insofar as they are relevant to anunderstanding of the present invention.

The memory 130 is a SDRAM bank, which again, is well known to the personskilled in the art.

As is conventional, the host controller, or embedded EHCI host, 140 isadapted to retrieve data which is prepared by the processor 120 in asuitable format, and to transmit the data over the bus interface. In USBcommunications, there are two categories of data transfer, namelyasynchronous transfer and periodic transfer. Control and bulk data aretransmitted using asynchronous transfer, and ISO and interrupt data aretransmitted using periodic transfer. The Enhanced Host ControllerInterface (EHCI) uses a Queue Transaction Descriptor (qTD) datastructure for asynchronous transfer, and an Isochronous TransactionDescriptor (iTD) data structure for periodic transfer.

In this case, the USB host 110 further includes a sub-system memory 180.The processor 120 prepares the data in the appropriate structure, andstores it in the sub-system memory 180, and the host controller 140 mustthen retrieve the data from the sub-system memory 180.

This means that the software stack running on the processor 120 does notneed to be changed significantly from the case in which the data isstored in the system memory 130, except that the data is directedinstead to the sub-system memory 180.

FIG. 2 shows in more detail the structure of the host controller 140.The host controller 140 includes an EHCI core 142, which is generallyconventional, and includes capability registers and operationalregisters 144, but will not be described further herein. The hostcontroller 140 is connected to an address decoder 148, which is alsogenerally conventional.

In accordance with the invention, the host controller 140 includes a DMAcontroller 150, which in FIG. 2 is shown in a single block with a busarbiter.

The DMA controller 150 is connected to a SDRAM controller 152, and canbe programmed with a start address 156 and a block length 158 by theEHCI core 142.

The EHCI core 42 of the host controller 40 uses the same transferdescriptors which are used in the conventional EHCI host controller,which retrieves data by mastering a PCI bus, and so the additionaleffort required to produce the EHCI core software is reduced.

The EHCI core 142 further includes a shared memory 162 in the form of aRAM.

Thus, when the host controller 140 initializes a transfer of data, astarting address and block length are sent from the core logic 142 tothe DMA controller 150, which can initiate a burst data transfer fromthe sub-system memory 180 to the RAM 162, from which it can betransmitted over the USB bus interface.

Because it is possible that the processor 120 will access the sub-systemmemory 180 at the same time as the host controller 140 is accessing thesub-system memory 180, it is necessary to be able to resolve anycontention.

When the host controller 140 is accessing the sub-system memory 180, thebus arbiter in the DMA controller 150 sends a Ready signal to theprocessor 120 to delay any attempt by the processor 120 to access thesub-system memory 180 until the host controller access is complete.

Further, an external data bus tri-state transceiver 190 is provided,connected between the host controller 140 the sub-system memory 180, andthe system memory 130. When the processor 120 is not accessing thesub-system memory 180, the data bus transceiver 190 is tri-stated, andthe host controller 140 accessing the sub-system memory 180 will notaffect the system memory 130. This can be controlled by a combination ofchip select and control signals from the processor 120.

Thus, FIG. 2 shows an architecture which requires an additional largesub-system memory, by comparison with the architecture of FIG. 1, butcan be used with a wider range of processors, since it does not requirethe processor to support bus arbitration.

1. An embedded host controller, for use in a USB system comprising aprocessor and an associated system memory coupled to the processor via abus, the host controller comprising: a DMA controller, the hostcontroller being adapted such that, in order to retrieve data from theassociated system memory, a starting address and a block length are sentto the DMA controller, wherein the host controller comprises aprogrammable register, the programmable register being adapted to storea signal received from the processor indicating a maximum number ofclock cycles for which the host controller can occupy the bus during abus access, and the DMA controller being adapted such that, on receiptof the starting address and the block length, the DMA controllerretrieves the indicated data from the associated system memory.
 2. Anembedded host controller as claimed in claim 1, wherein the DMAcontroller is adapted to send a bus request to the processor, and toretrieve data from the associated system memory only when bus access hasbeen granted.
 3. An embedded host controller as claimed in claim 1,wherein the host controller is adapted to release the bus on expiry ofthe maximum number of clock cycles.
 4. An embedded host controller asclaimed in claim 1, wherein the associated system memory is a SDRAM, andthe host controller comprises a SDRAM controller, the SDRAM controllerbeing adapted to perform a refresh function if retrieval of theindicated data from the associated system memory takes longer than arefresh period of the SDRAM.
 5. An embedded host controller as claimedin claim 1, wherein the DMA controller is adapted to send a signal tothe processor while the DMA controller is retrieving data from theassociated system memory, the signal to prevent the processor fromsimultaneously attempting to access the associated system memory.
 6. AUSB host, comprising: a processor, wherein the processor is adapted togrant bus access on a bus; a system memory, to which the processorwrites USB data via the bus, wherein the associated system memory is aSDRAM; and a host controller, the host controller comprising: a DMAcontroller, and the host controller being adapted such that, in order toretrieve data from the system memory, a starting address and a blocklength are sent to the DMA controller, and the DMA controller beingadapted such that, on receipt of the starting address and the blocklength, the DMA controller sends a bus request to the processor, andretrieves data from the system memory only when bus access has beengranted, and a SDRAM controller, the SDRAM controller being adapted toperform a refresh function if retrieval of the indicated data from theassociated system memory takes longer than a refresh period of theSDRAM.
 7. A USB host as claimed in claim 6, wherein the processor isadapted to send to the host controller a maximum duration signalindicating a maximum number of clock cycles for which the hostcontroller can occupy the bus during a bus access, and wherein the hostcontroller comprises a programmable register, the programmable registerbeing adapted to store the maximum duration signal received from theprocessor.
 8. A USB host as claimed in claim 7, wherein the hostcontroller is adapted to release the bus on expiry of the maximum numberof clock cycles.
 9. A USB host, comprising: a processor; a systemmemory; a sub-system memory, to which the processor writes USB data; anda host controller, the host controller comprising: a DMA controller, andthe host controller being adapted such that, in order to retrieve datafrom the sub-system memory, a starting address and a block length aresent to the DMA controller, and the DMA controller being adapted suchthat, on receipt of the starting address and the block length, the DMAcontroller retrieves the indicated data from the sub-system memory, theDMA controller being further adapted to send a signal to the processorwhile the DMA controller is retrieving data from the sub-system memory,the signal to prevent the processor from simultaneously attempting toaccess the sub-system memory.
 10. A USB host as claimed in claim 9,wherein the DMA controller is adapted to send a signal to the processorwhile the DMA controller is retrieving data from the associated systemmemory, the signal to prevent the processor from simultaneouslyattempting to access the associated system memory.
 11. A USB host asclaimed in claim 9, wherein the signal comprises a ready signal from abus arbiter in the DMA controller, the ready signal to delay an attemptby the processor to access the sub-system memory.
 12. A USB host asclaimed in claim 9, further comprising a tri-state transceiver coupledto the host controller and the sub-system memory, the tri-statetransceiver to enter a tri-state mode when the processor is notaccessing the sub-system memory.
 13. A USB host as claimed in claim 9,wherein the DMA controller is adapted to retrieve the indicated datafrom the sub-system memory when the processor does not provide busarbitration.